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your imagination, our creation GL711FW ata/atapi to 1394 native bridge two in one solution specification 1.3 sep. 12, 2001 genesy s logic, inc. 10f, no. 11, ln. 155, sec. 3, peishen rd., taipei, taiwan tel: (886 2) 2664 6655 fax: (886 2) 2664 5757 http://www.genesyslogic.com
GL711FW -1- revision: 1.3 09/12/2001 index 1. overview .....................................................................................2 2. features .......................................................................................3 3. function block ............................................................................4 4. system conf iguration .................................................................7 5. pin confi guration ......................................................................11 6. electrical ch aracteristics ..........................................................15 7. package di mension ...................................................................16
GL711FW -2- revision: 1.3 09/12/2001 1. overview the GL711FW is a high-performance 1394 to ata/atapi native bridge with an embedded sbp-2 target solution. it supports a solution for link/transaction layer controller conforming to the ieee std 1394 (ieee 1394-1995 and ieee 1394.a) up to 400mbps transfer rate. through the sbp-2 port driver, supported by microsoft windows 2000 and windows 98 se, windows me, scsi class drivers can use sbp-2 to communicate with ieee 1394 device using the scsi command set. by means of the embedded 8052 processor running the firmware located in rom (internal or optionally external) GL711FW provides an sbp-2 protocol engine to automatically achieve the transport of scsi command and data over ieee std 1394 serial bus. GL711FW provides a memory interface for reading/writi ng firmware from/to external flash rom, so that it makes software download easily and helps testing, development, or other specific application purpose. GL711FW also supports an 8051 interface, which allows external 8051 to access the internal memory when the embedded 8052 was disabled for debugging and testing. the GL711FW is ideally suited to hard disk drives (hdds), mo, cd-rom, cd-r, cd-rw and dvd. it allows ide drives being able to connect to a 1394 serial bus in a plug-and-play fashion. the ata/atapi interface of GL711FW supports signal timing up to ultra-dma mode 5.
GL711FW -3- revision: 1.3 09/12/2001 2. features
GL711FW 3. function block block diagram ide interface auto packet di st ri but or adp state machine auto packet generator 1394.a link core tx/rx fifo (pi ng-pong buffer) (2k by t e s * 2) sbp-2 registers mo p cop pte morb corb asy n . tx reg i sters asy n . rx reg i sters 1394 c ont rol reg i sters ide ultra dma engine i/o reg i sters em bedded 8052 micro-controller GL711FW -4- rev i sion: 1.3 09/ 12/ 2001
GL711FW -5- revision: 1.3 09/12/2001 functional overview the GL711FW is designed to simplify the firmware issue of GL711FW architecture: 1. asyn tx registers: general asynchronous packet transmit registers, 4-quadlets for 1394 header and 8-quadlets for data payload. afte r getting all fields of packet ready, the firmware can set ?asyntx? instruction to send the packet. some packets for transmitting packets like ?login response?, ?query login response? and ?status block? are prepared by the registers whose maximum data payload is 8 quadlets. 2. asyn rx registers: general asynchronous packet receives registers, 4-quadlets for 1394 header and 8-quadlets for data payload. the received packet other than the sbp-2 associated read response packets, like "config rom read request" from the initiators, is stored in the registers. however, all the sbp-2 read response packet received from the initiators are always expected by the target and forwarded to the auto packet distributor. 3. 1394 control registers: control and interrupt register s for ieee 1394 and sbp-2 protocol, see the details in the section of 1394 control register. 4. adp state machine: automatic data pipe control for sb p-2 data transfer and page table fetch. 5. auto packet generator: generate the read or write request packet header of those packets with standard format like config rom r ead response packet, management orb read request, command orb read request, page tabl e read request, block data read request from or write request to initiator. 6. auto packet distributor: the data payload of sbp-2 associated packet is stored at the specified registers according to its destinati on offset, tlabel or last request packet command. the received data payload is classified by the GL711FW to 7 types:
GL711FW -6- revision: 1.3 09/12/2001 management orb agent pointer (2 quadlets), command orb agent pointer (2 quadlets), management orb (8 quadlets), command orb (8 quadlets), page table pointer (2 quadlets), general rx data payload (8 quadlets) , and general data moved from or to initiator (1k quadlets). 7. sbp-2 registers: the registers for received data payload of sbp-2 associated packet including management orb agent pointer (2 quadlets), command orb agent pointer (2 quadlets), management orb (8 quadlets) , command orb (8 quadlets) and page table pointer (2 quadlets). 8. tx/rx data fifo: 4 kbytes of ping-pong buffer for data moved between the initiator and target. 9. ide ultra dma engine: control the interface to ide device and automatically access data with ide dma or ide udma mode. 10. i/o control registers: a register space to store information about status, packet and chip, accessible by system asic and ide interface: an interface for accessing ide device internal registers. 12. 8051 micro-controller : an embedded processor for sbp2-2 to ata/atapi command transaction.
GL711FW 4. system configuration system diagram udma 100 inter f ace ata/atapi storage devices i e e e 1394 phy controller flash rom (optional) GL711FW 1394 i n terface -7- rev i sion: 1.3 09/ 12/ 2001
GL711FW embedded 8052 enabled and run the internal rom code. linkon phylps phyclk phyd [ 7: 0 ] phyctl [ 1: 0 ] phylre q ide device hdcs1# hdintr hdd [ 15: 0 ] hda [ 2: 0 ] hdcs0# hdw r# hdrd# ready# hddack# hddr q ieee 1394 phy controller GL711FW ata/atapi to 1394 native bridge -8- rev i sion: 1.3 09/ 12/ 2001
GL711FW e m b e d d e d 8 0 5 2 e n a b l e d a n d l o a d t h e e x t e r n a l e e p r o m c o d e . we # ad [ 7: 0 ] linkon phylps phyclk phyd [ 7: 0 ] phyctl [ 1: 0 ] phylre q oe# addr [ 15: 0 ] ide device hdcs1# hdintr hdd [ 15: 0 ] hda [ 2: 0 ] hdcs0# hdw r# hdrd# ready# hddack# hddr q ieee 1394 phy controller GL711FW ata/atapi to 1394 native bridge eeprom -9- rev i sion: 1.3 09/ 12/ 2001
GL711FW d i s a b l e e m b e d d e d 8 0 5 2 . ide device p (8051) GL711FW ata/atapi to 1394 native bridge ieee 1394 phy controller hdcs1# hda [ 2: 0 ] hdd [ 15: 0 ] hdintr ad [ 7: 0 ] ale rd# wr # int# phylre q phyctl [ 1: 0 ] phyd [ 7: 0 ] phyclk phylps cs# linkon hdcs0# hdw r# hdrd# ready# hddack# hddr q -10- rev i sion: 1.3 09/ 12/ 2001
GL711FW 5. pin configuration pin assignment t est 19 ph y d 7 6 hd int 42 a ddr 1 3 87 vd d 29 vd d 76 vd d 2 hdd 1 1 59 en u p # 69 ea 70 gn d 21 ad 6 3 vd d 86 hdd 1 0 61 a d dr5 78 GL711FW hd io w# 46 a d dr1 73 gn d 5 ph y d 4 9 ph y d 0 14 p1 1 24 en i d e # 22 p1 6 30 a ddr 1 1 91 p1 4 34 vd d 54 gn d 35 p1 3 80 ad 4 10 0 dm a 1 6 94 hd d0 49 cs # 95 ph y c l k 17 hd da 1 40 p1 7 68 p1 2 32 a d dr4 77 ad 7 4 lr eq 18 hd d4 60 int # 27 hdd 1 3 53 hd d6 65 hd io r # 45 hd d1 52 hd d8 66 r ese t # 31 hd da 2 38 ad 5 1 gn d 57 ph y c t l 0 16 hdd 1 4 51 vd d 41 a ddr 1 5 81 hd da ck # 43 hd dr q 47 ph y d 5 8 a d dr9 89 a d dr8 88 a ddr 1 0 93 vd d 10 ph y d 3 11 gn d 50 vd d 62 wr # 25 hd da 0 39 ph y d 1 13 a d dr7 82 a ddr 1 2 83 gn d 90 hd d2 55 a d dr3 75 o e # / rd# 92 ph y d 6 7 a d dr0 72 ad 2 98 hd d5 63 ad 0 96 hdd 1 2 56 ad 1 97 al e 26 hd d1 5 48 gn d 71 p1 5 28 a ddr 1 4 33 hd d9 64 a d dr2 74 ph y d 2 12 hd d7 67 hd d3 58 ph y c t l 1 15 p1 0 23 a d dr6 79 we # 85 ad 3 99 sc an e n 20 hd cs 0 # 37 hd io r d y 44 hd cs 1 # 36 gn d 84 -11- rev i sion: 1.3 09/ 12/ 2001
GL711FW -12- revision: 1.3 09/12/2001 pin description pin symbol i/o description power 31 reset# i master reset signal, low active 2,10,29, 41,54,62, 76,86 vcc - 3.3v power supply 5,21,35, 50,57,71, 84,90 gnd - ground signals for micro-processor 92 oe#/rd# i/o when enup# = ?1?: this active low signal enables the reading of internal register. when enup# = ?0?: this bit is used for output enable flash memory output 25 wr# i up: this active low signal enables the writing of internal register. 1,3,4, 96-100 ad0-ad7 i/o when enup# = ?1?: address & data bus bit 0 to bit 7 of external device i/o write (for pio and multi-word dma mode) stop ultra dma burst (for udma mode)
GL711FW -13- revision: 1.3 09/12/2001 45 hdior#(hd mardy#/, hdstrobe) o device i/o read (for pio and multi-word dma mode) ultra dma host ready (for udma read) ultra dma host data strobe (for udma write) 48,51,53, 56,59,61, 64,66,67, 65,63,60, 58,55,52, 49 hdd15-0 i/o ide device data. the 8- or 16-bit data bus to/from the ata device. only the lower 8 bits are used for 8-bit register transfers. 44 hdiordy(d dmardy#/, dstrobe) i i/o channel ready (for pio and multi-word dma mode) ultra dma device ready (for udma write) ultra dma device data strobe (for udma read) 42 hdint i ide device interrupt: this input signal is used to interrupt the host system when interrupt pending is set. 43 hddack# o ide dma acknowledge: this signal is used by the ata host to response dmarq for dma transfers. 47 hddrq i ide dma request: this signal is asserted by the ata device when it is ready to perform a dma data transfer to or from the ata host when a dma operation has been enabled. signals for phy-interface 15,16 phy_ctl1 phy_ctl0 i/o control 1 and control 0 of the phy-link control bus. ctl1 and ctl0 indicate the four operations that can occur in this interface. 18 lreq o link request. lreq is a output that make s bus requests and accesses the phy layer. 6-9,11-14 phy_d7-0 i/o phy data7 through data0 of the phy-link data bus. data is expected on d0-d1 for 100mb/s packets, d0-d3 for 200mb/s, and d0-d7 for 400mb/s. 17 phy_sclk i system clock. phy_sclk is a 49.152-mhz clock from the phy. signals for flash memory 81,33,87, 83,91,93, 89,88,82, 79,78,77, 75,74,73, 72 addr[15:0] o flash prom /eprom address bus. addr15 is the most significant bit.
GL711FW -14- revision: 1.3 09/12/2001 85 we# o flash prom/eprom write enable(active low). during normal operation this bit is asserting high. miscellaneous signals 68,30,28, 34,80,32, 24,23 p17-p10 i/o gpio for firmware use 94 dma16 i this bit is used to enable 16-bits dma function. 19 test i this bit is used only in test mode. this bit must tie low in normal . 20 scanen i this bit is used only in test mode. this bit must tie low in normal . 22 enide# i for enable ide function, active low. 69 enup# i for enable internal 8052 function, active low. 70 ea i for enable external rom.
GL711FW -15- revision: 1.3 09/12/2001 6. electrical characteristics absolute maximum ratings supply voltage range, (vcc) -0.3v to 3.6v input voltage range -0.3v to (vcc+0.3v) output voltage range -0.3v to (vcc+0.3v) operating temperature 0 recommended operation conditions nom. min. max. uiits supply voltage 3.3 3.0 3.6 v input voltage 0 vcc v output voltage vcc v high-level input voltage, vih 0.7vcc vcc v low-level input voltage, vil 0 0.3vcc v operating temperature 25 0 70 0 electrical characteristics parameter test conditions min. max. uiits high-level output voltage, voh ioh = -12ma ioh= -8ma 0.8vcc v low-level output voltage, vol iol = 12ma iol= 8ma 0.2vcc v
GL711FW 7. pack age dimension -16- rev i sion: 1.3 09/ 12/ 2001

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